TIM8EN=B_0x0, SPI1EN=B_0x0, TIM17EN=B_0x0, LTDCEN=B_0x0, TIM1EN=B_0x0, SAI2EN=B_0x0, TIM15EN=B_0x0, TIM16EN=B_0x0, USART1EN=B_0x0, SAI1EN=B_0x0, GFXTIMEN=B_0x0, USBEN=B_0x0, DSIEN=B_0x0
RCC APB2 peripheral clock enable register
| TIM1EN | TIM1 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM1 clock disabled 1 (B_0x1): TIM1 clock enabled |
| SPI1EN | SPI1 clock enable This bit is set and cleared by software. 0 (B_0x0): SPI1 clock disabled 1 (B_0x1): SPI1 clock enabled |
| TIM8EN | TIM8 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM8 clock disabled 1 (B_0x1): TIM8 clock enabled |
| USART1EN | USART1clock enable This bit is set and cleared by software. 0 (B_0x0): USART1 clock disabled 1 (B_0x1): USART1 clock enabled |
| TIM15EN | TIM15 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM15 clock disabled 1 (B_0x1): TIM15 clock enabled |
| TIM16EN | TIM16 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM16 clock disabled 1 (B_0x1): TIM16 clock enabled |
| TIM17EN | TIM17 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM17 clock disabled 1 (B_0x1): TIM17 clock enabled |
| SAI1EN | SAI1 clock enable This bit is set and cleared by software. 0 (B_0x0): SAI1 clock disabled 1 (B_0x1): SAI1 clock enabled |
| SAI2EN | SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): SAI2 clock disabled 1 (B_0x1): SAI2 clock enabled |
| USBEN | USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USB clock disabled 1 (B_0x1): USB clock enabled |
| GFXTIMEN | GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GFXTIM clock disabled 1 (B_0x1): GFXTIM clock enabled |
| LTDCEN | LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): LTDC clock disabled 1 (B_0x1): LTDC clock enabled |
| DSIEN | DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DSI clock disabled 1 (B_0x1): DSI clock enabled |