LSERDYF=B_0x0, CSSF=B_0x0, SHSIRDYF=B_0x0, MSIKRDYF=B_0x0, PLL2RDYF=B_0x0, HSIRDYF=B_0x0, LSIRDYF=B_0x0, PLL1RDYF=B_0x0, HSERDYF=B_0x0, PLL3RDYF=B_0x0, MSISRDYF=B_0x0, HSI48RDYF=B_0x0
RCC clock interrupt flag register
| LSIRDYF | LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software by�setting the LSIRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the LSI oscillator 1 (B_0x1): Clock ready interrupt caused by the LSI oscillator |
| LSERDYF | LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit. 0 (B_0x0): No clock ready interrupt caused by the LSE oscillator 1 (B_0x1): Clock ready interrupt caused by the LSE oscillator |
| MSISRDYF | MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. It�is cleared by software by setting the MSISRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the MSIS oscillator 1 (B_0x1): Clock ready interrupt caused by the MSIS oscillator |
| HSIRDYF | HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 in�response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSI16 oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI16 oscillator |
| HSERDYF | HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSE oscillator 1 (B_0x1): Clock ready interrupt caused by the HSE oscillator |
| HSI48RDYF | HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. it�is cleared by software by setting the HSI48RDYC bit. 0 (B_0x0): No clock ready interrupt caused by the HSI48 oscillator 1 (B_0x1): Clock ready interrupt caused by the HSI48 oscillator |
| PLL1RDYF | PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit. 0 (B_0x0): No clock ready interrupt caused by PLL1 lock 1 (B_0x1): Clock ready interrupt caused by PLL1 lock |
| PLL2RDYF | PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit. 0 (B_0x0): No clock ready interrupt caused by PLL2 lock 1 (B_0x1): Clock ready interrupt caused by PLL2 lock |
| PLL3RDYF | PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit. 0 (B_0x0): No clock ready interrupt caused by PLL3 lock 1 (B_0x1): Clock ready interrupt caused by PLL3 lock |
| CSSF | Clock security system interrupt flag This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit. 0 (B_0x0): No clock security interrupt caused by HSE clock failure 1 (B_0x1): Clock security interrupt caused by HSE clock failure |
| MSIKRDYF | MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the MSIK oscillator 1 (B_0x1): Clock ready interrupt caused by the MSIK oscillator |
| SHSIRDYF | SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit. 0 (B_0x0): No clock ready interrupt caused by the SHSI oscillator 1 (B_0x1): Clock ready interrupt caused by the SHSI oscillator |