HSION=B_0x0, PLL1RDY=B_0x0, HSIKERON=B_0x0, MSISON=B_0x0, HSERDY=B_0x0, MSIKON=B_0x0, HSEBYP=B_0x0, HSEEXT=B_0x0, PLL2ON=B_0x0, PLL1ON=B_0x0, PLL3RDY=B_0x0, PLL2RDY=B_0x0, HSI48RDY=B_0x0, PLL3ON=B_0x0, HSI48ON=B_0x0, HSEON=B_0x0, MSIPLLFAST=B_0x0, MSIPLLSEL=B_0x0, MSIKRDY=B_0x0, MSIPLLEN=B_0x0, SHSIRDY=B_0x0, MSISRDY=B_0x0, MSIKERON=B_0x0, HSIRDY=B_0x0, SHSION=B_0x0, CSSON=B_0x0
RCC clock control register
| MSISON | MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the�MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock. 0 (B_0x0): MSIS (MSI system) oscillator off 1 (B_0x1): MSIS (MSI system) oscillator on |
| MSIKERON | MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Section�11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode. 0 (B_0x0): No effect on MSI oscillator 1 (B_0x1): MSI oscillator forced ON even in Stop mode |
| MSISRDY | MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. 0 (B_0x0): MSIS (MSI system) oscillator not ready 1 (B_0x1): MSIS (MSI system) oscillator ready |
| MSIPLLEN | MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). 0 (B_0x0): MSI PLL-mode OFF 1 (B_0x1): MSI PLL-mode ON |
| MSIKON | MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCK�=�0 when exiting Stop modes, or in case of a failure of the HSE oscillator. 0 (B_0x0): MSIK (MSI kernel) oscillator disabled 1 (B_0x1): MSIK (MSI kernel) oscillator enabled |
| MSIKRDY | MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. 0 (B_0x0): MSIK (MSI kernel) oscillator not ready 1 (B_0x1): MSIK (MSI kernel) oscillator ready |
| MSIPLLSEL | MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI output clock uses the PLL mode. It�can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs. 0 (B_0x0): PLL mode applied to MSIK (MSI kernel) clock output 1 (B_0x1): PLL mode applied to MSIS (MSI system) clock output |
| MSIPLLFAST | MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The�fast start-up is active when the MSI in PLL mode returns from switch off. 0 (B_0x0): MSI PLL normal start-up 1 (B_0x1): MSI PLL fast start-up |
| HSION | HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the�HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 0 (B_0x0): HSI16 oscillator off 1 (B_0x1): HSI16 oscillator on |
| HSIKERON | HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Section�11.4.24 for more details. This bit must be configured at 0 before entering Stop 3 mode. 0 (B_0x0): No effect on HSI16 oscillator 1 (B_0x1): HSI16 oscillator forced on even in Stop mode |
| HSIRDY | HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles. 0 (B_0x0): HSI16 oscillator not ready 1 (B_0x1): HSI16 oscillator ready |
| HSI48ON | HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes. 0 (B_0x0): HSI48 oscillator off 1 (B_0x1): HSI48 oscillator on |
| HSI48RDY | HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON). 0 (B_0x0): HSI48 oscillator not ready 1 (B_0x1): HSI48 oscillator ready |
| SHSION | SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes. 0 (B_0x0): SHSI oscillator off 1 (B_0x1): SHSI oscillator on |
| SHSIRDY | SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. 0 (B_0x0): SHSI oscillator not ready 1 (B_0x1): SHSI oscillator ready |
| HSEON | HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0 (B_0x0): HSE oscillator off 1 (B_0x1): HSE oscillator on |
| HSERDY | HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. 0 (B_0x0): HSE oscillator not ready 1 (B_0x1): HSE oscillator ready |
| HSEBYP | HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with an external clock. The�external clock must be enabled with the HSEON bit set, to be used by the device. This�bit can be written only if the HSE oscillator is disabled. 0 (B_0x0): HSE crystal oscillator not bypassed 1 (B_0x1): HSE crystal oscillator bypassed with external clock |
| CSSON | Clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 0 (B_0x0): clock security system OFF (clock detector OFF) 1 (B_0x1): clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not). |
| HSEEXT | HSE external clock bypass mode This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. 0 (B_0x0): external HSE clock analog mode 1 (B_0x1): external HSE clock digital mode (through I/O Schmitt trigger) |
| PLL1ON | PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. 0 (B_0x0): PLL1 OFF 1 (B_0x1): PLL1 ON |
| PLL1RDY | PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked. 0 (B_0x0): PLL1 unlocked 1 (B_0x1): PLL1 locked |
| PLL2ON | PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 0 (B_0x0): PLL2 OFF 1 (B_0x1): PLL2 ON |
| PLL2RDY | PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked. 0 (B_0x0): PLL2 unlocked 1 (B_0x1): PLL2 locked |
| PLL3ON | PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 0 (B_0x0): PLL3 OFF 1 (B_0x1): PLL3 ON |
| PLL3RDY | PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked. 0 (B_0x0): PLL3 unlocked 1 (B_0x1): PLL3 locked |