STMicroelectronics /STM32U5Fx /RCC /RCC_SECCFGR

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Interpret as RCC_SECCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HSISEC 0 (B_0x0)HSESEC 0 (B_0x0)MSISEC 0 (B_0x0)LSISEC 0 (B_0x0)LSESEC 0 (B_0x0)SYSCLKSEC 0 (B_0x0)PRESCSEC 0 (B_0x0)PLL1SEC 0 (B_0x0)PLL2SEC 0 (B_0x0)PLL3SEC 0 (B_0x0)ICLKSEC 0 (B_0x0)HSI48SEC 0 (B_0x0)RMVFSEC

ICLKSEC=B_0x0, RMVFSEC=B_0x0, LSESEC=B_0x0, LSISEC=B_0x0, HSESEC=B_0x0, PRESCSEC=B_0x0, PLL2SEC=B_0x0, MSISEC=B_0x0, SYSCLKSEC=B_0x0, HSI48SEC=B_0x0, HSISEC=B_0x0, PLL3SEC=B_0x0, PLL1SEC=B_0x0

Description

RCC secure configuration register

Fields

HSISEC

HSI clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

HSESEC

HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

MSISEC

MSI clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

LSISEC

LSI clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

LSESEC

LSE clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

SYSCLKSEC

SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

PRESCSEC

AHBx/APBx prescaler configuration bits security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

PLL1SEC

PLL1 clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

PLL2SEC

PLL2 clock configuration and status bit security Set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

PLL3SEC

PLL3 clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

ICLKSEC

Intermediate clock source selection security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

HSI48SEC

HSI48 clock configuration and status bit security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

RMVFSEC

Remove reset flag security This bit is set and reset by software.

0 (B_0x0): non secure

1 (B_0x1): secure

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