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STMicroelectronics /STM32U5Gx /DSI /DSI_CLTCR

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Interpret as DSI_CLTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LP2HS_TIME0HS2LP_TIME

Description

DSI Host clock lane timer configuration register

Fields

LP2HS_TIME

Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from low‑power to high-speed transmission measured in lane byte clock cycles.
HS2LP_TIME

High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from high‑speed to low-power transmission measured in lane byte clock cycles.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data