STMicroelectronics /STM32U5Gx /DSI /DSI_DLTRCR

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Interpret as DSI_DLTRCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MRD_TIME

Description

DSI Host data lane timer read configuration register

Fields

MRD_TIME

Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.

Links

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