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STMicroelectronics /STM32U5Gx /DSI /DSI_DPDL0SRCR

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Interpret as DSI_DPDL0SRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SRC

Description

DSI D-PHY data lane 0 skew rate control register

Fields

SRC

Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved

14 (B_0xE): 80 to 750 Mbit/s

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data