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STMicroelectronics /STM32U5Gx /DSI /DSI_LPCR

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Interpret as DSI_LPCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DEP 0 (B_0x0)VSP 0 (B_0x0)HSP

DEP=B_0x0, VSP=B_0x0, HSP=B_0x0

Description

DSI Host LTDC polarity configuration register

Fields

DEP

Data enable polarity This bit configures the polarity of data enable pin.

0 (B_0x0): Data enable pin active high (default)

1 (B_0x1): Data enable pin active low
VSP

VSYNC polarity This bit configures the polarity of VSYNC pin.

0 (B_0x0): Shutdown pin active high (default)

1 (B_0x1): Shutdown pin active low
HSP

HSYNC polarity This bit configures the polarity of HSYNC pin.

0 (B_0x0): HSYNC pin active high (default)

1 (B_0x1): VSYNC pin active low

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data