Regviz

STMicroelectronics /STM32U5Gx /DSI /DSI_TCCR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_TCCR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32U599/DSI/DSI_TCCR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HSRD_TOCNT

Description

DSI Host timeout counter configuration register 1

Fields

HSRD_TOCNT

High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data