STMicroelectronics /STM32U5Gx /DSI /DSI_WRPCR

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Interpret as DSI_WRPCR

ODF=B_0x0, IDF=B_0x0, PLLEN=B_0x0, NDIV=B_0x0

Description

DSI Wrapper regulator and PLL control register

Fields

PLLEN	PLL enable This bit enables the D-PHY PLL. 0 (B_0x0): PLL disabled 1 (B_0x1): PLL enabled
NDIV	PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 … 511: PLL loop divided by 511x2 0 (B_0x0): PLL loop divided by 1x2 1 (B_0x1): PLL loop divided by 1x2
IDF	PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 … 511: PLL input divided by 511 0 (B_0x0): PLL input divided by 1 1 (B_0x1): PLL input divided by 1
ODF	PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 … 511: PLL output divided by 511 0 (B_0x0): PLL output divided by 1 1 (B_0x1): PLL output divided by 1

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