TEPOL=B_0x0, TES=B_0x0, SYNCS=B_0x0, LCCOE=B_0x0, FCCOE=B_0x0
GFXTIM configuration register
| TES | tearing source This field selects the tearing-effect source. 0 (B_0x0): TE input pad selected 1 (B_0x1): gfxtim_ite selected 2 (B_0x2): HSYNC input selected by SYNCS[1:0] 3 (B_0x3): VSYNC input selected by SYNCS[1:0] |
| TEPOL | tearing–effect polarity This bit selects the tearing-effect polarity. 0 (B_0x0): tearing effect active on rising edge 1 (B_0x1): tearing effect active on falling edge |
| SYNCS | synchronization source This field selects the synchronization signals (HSYNC and VSYNC) sources. 0 (B_0x0): gfxtim_hsync[0] and gfxtim_vsync[0] selected 1 (B_0x1): gfxtim_hsync[1] and gfxtim_vsync[1] selected 2 (B_0x2): gfxtim_hsync[2] and gfxtim_vsync[2] selected 3 (B_0x3): gfxtim_hsync[3] and gfxtim_vsync[3] selected |
| FCCOE | frame-clock calibration output enable This bit enables the frame-clock output. 0 (B_0x0): frame-clock output disabled 1 (B_0x1): frame-clock output enabled |
| LCCOE | line-clock calibration output enable This bit enables the line-clock output. 0 (B_0x0): line-clock output disabled 1 (B_0x1): line-clock output enabled |