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STMicroelectronics /STM32U5Gx /GFXTIM /GFXTIM_TDR

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Interpret as GFXTIM_TDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)AFCDIS 0 (B_0x0)ALCDIS 0 (B_0x0)RFC1DIS 0 (B_0x0)RFC2DIS

RFC2DIS=B_0x0, RFC1DIS=B_0x0, ALCDIS=B_0x0, AFCDIS=B_0x0

Description

GFXTIM timers disable register

Fields

AFCDIS

absolute frame counter disable This bit disables the absolute frame counter.

0 (B_0x0): no effect

1 (B_0x1): absolute frame counter disabled
ALCDIS

absolute line counter disable This bit disables the absolute line counter.

0 (B_0x0): no effect

1 (B_0x1): absolute line counter disabled
RFC1DIS

relative frame counter 1 disable This bit disables the relative frame counter 1.

0 (B_0x0): no effect

1 (B_0x1): relative frame counter 1 disabled
RFC2DIS

relative frame counter 2 disable This bit disables the relative frame counter 2.

0 (B_0x0): no effect

1 (B_0x1): relative frame counter 2 disabled

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data