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STMicroelectronics /STM32U5Gx /GFXTIM /GFXTIM_TSR

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Interpret as GFXTIM_TSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)AFCS 0 (B_0x0)ALCS 0 (B_0x0)RFC1S 0 (B_0x0)RFC2S

ALCS=B_0x0, RFC2S=B_0x0, RFC1S=B_0x0, AFCS=B_0x0

Description

GFXTIM timers status register

Fields

AFCS

absolute frame counter status This bit returns the status of the absolute frame counter.

0 (B_0x0): absolute frame counter disabled

1 (B_0x1): absolute frame counter enabled
ALCS

absolute line counter status This bit returns the status of the absolute line counter.

0 (B_0x0): absolute line counter disabled

1 (B_0x1): absolute line counter enabled
RFC1S

relative frame counter 1 status This bit returns the status of the relative frame counter 1.

0 (B_0x0): relative frame counter 1 disabled

1 (B_0x1): relative frame counter 1 enabled
RFC2S

relative frame counter 2 status This bit returns the status of the relative frame counter 2.

0 (B_0x0): relative frame counter 2 disabled

1 (B_0x1): relative frame counter 2 enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data