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STMicroelectronics /STM32U5Gx /GTZC2_MPCBB4 /MPCBB4_CR

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Interpret as MPCBB4_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GLOCK)GLOCK 0 (INVSECSTATE)INVSECSTATE 0 (SRWILADIS)SRWILADIS

Description

MPCBB control register

Fields

GLOCK

lock the control register of the MPCBB until next reset
INVSECSTATE

SRAMx clocks security state
SRWILADIS

secure read/write illegal access disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data