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STMicroelectronics /STM32U5Gx /LPTIM1 /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IN1SEL 0IN2SEL 0IC1SEL 0IC2SEL

Description

LPTIM configuration register 2

Fields

IN1SEL

LPTIM input 1 selection
IN2SEL

LPTIM input 2 selection
IC1SEL

LPTIM input capture 1 selection
IC2SEL

LPTIM input capture 2 selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data