RRIE=B_0x0, FUIE=B_0x0, TERRIE=B_0x0, LIE=B_0x0
LTDC interrupt enable register
| LIE | line interrupt enable This bit is set and cleared by software. 0 (B_0x0): line interrupt disable 1 (B_0x1): line interrupt enable |
| FUIE | FIFO underrun interrupt enable This bit is set and cleared by software. 0 (B_0x0): FIFO underrun interrupt disable 1 (B_0x1): FIFO underrun Interrupt enable |
| TERRIE | transfer error interrupt enable This bit is set and cleared by software. 0 (B_0x0): transfer error interrupt disable 1 (B_0x1): transfer error interrupt enable |
| RRIE | register reload interrupt enable This bit is set and cleared by software. 0 (B_0x0): register reload interrupt disable 1 (B_0x1): register reload interrupt enable |