STMicroelectronics /STM32U5Gx /OTG_HS /DIEPMSK

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Interpret as DIEPMSK

31282724232019161512118743000000000000000000000000000000000000000000 (XFRCM)XFRCM0 (EPDM)EPDM0 (AHBERRM)AHBERRM0 (TOM)TOM0 (ITTXFEMSK)ITTXFEMSK0 (INEPNMM)INEPNMM0 (INEPNEM)INEPNEM0 (TXFURM)TXFURM0 (NAKM)NAKM

Description

This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.

Fields

XFRCM

XFRCM

EPDM

EPDM

AHBERRM

AHBERRM

TOM

TOM

ITTXFEMSK

ITTXFEMSK

INEPNMM

INEPNMM

INEPNEM

INEPNEM

TXFURM

TXFURM

NAKM

NAKM

Links

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