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STMicroelectronics /STM32U5Gx /PWR /PWR_BDCR2

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Interpret as PWR_BDCR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)VBE 0 (B_0x0)VBRS

VBRS=B_0x0, VBE=B_0x0

Description

PWR Backup domain control register 2

Fields

VBE

VBAT charging enable

0 (B_0x0): VBAT battery charging disabled

1 (B_0x1): VBAT battery charging enabled
VBRS

VBAT charging resistor selection

0 (B_0x0): Charge VBAT through a 5 kΩ resistor

1 (B_0x1): Charge VBAT through a 1.5 kΩ resistor

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data