DCACHE2SMEN=B_0x0, DMA2DSMEN=B_0x0, GFXMMUSMEN=B_0x0, DCACHE1SMEN=B_0x0, ICACHESMEN=B_0x0, MDF1SMEN=B_0x0, RAMCFGSMEN=B_0x0, FMACSMEN=B_0x0, GPDMA1SMEN=B_0x0, GTZC1SMEN=B_0x0, BKPSRAMSMEN=B_0x0, TSCSMEN=B_0x0, GPU2DSMEN=B_0x0, SRAM1SMEN=B_0x0, JPEGSMEN=B_0x0, CORDICSMEN=B_0x0, FLASHSMEN=B_0x0, CRCSMEN=B_0x0
RCC AHB1 peripheral clock enable in Sleep and Stop modes register
| GPDMA1SMEN | GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): GPDMA1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GPDMA1 clocks enabled by the clock gating during Sleep and Stop modes |
| CORDICSMEN | CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sleep mode. 0 (B_0x0): CORDIC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): CORDIC clocks enabled by the clock gating during Sleep and Stop modes |
| FMACSMEN | FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software. 0 (B_0x0): FMAC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): FMAC clocks enabled by the clock gating during Sleep and Stop modes |
| MDF1SMEN | MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): MDF1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): MDF1 clocks enabled by the clock gating during Sleep and Stop modes |
| FLASHSMEN | FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): FLASH clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): FLASH clocks enabled by the clock gating during Sleep and Stop modes |
| CRCSMEN | CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): CRC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): CRC clocks enabled by the clock gating during Sleep and Stop modes |
| JPEGSMEN | JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): JPEG clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): JPEG clocks enabled by the clock gating during Sleep and Stop modes |
| TSCSMEN | TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): TSC clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TSC clocks enabled by the clock gating during Sleep and Stop modes |
| RAMCFGSMEN | RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): RAMCFG clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): RAMCFG clocks enabled by the clock gating during Sleep and Stop modes |
| DMA2DSMEN | DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DMA2D clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DMA2D clocks enabled by the clock gating during Sleep and Stop modes |
| GFXMMUSMEN | GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GFXMMU clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GFXMMU clocks enabled by the clock gating during Sleep and Stop modes |
| GPU2DSMEN | GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): GPU2D clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GPU2D clocks enabled by the clock gating during Sleep and Stop modes |
| DCACHE2SMEN | DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): DCACHE2 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DCACHE2 clocks enabled by the clock gating during Sleep and Stop modes |
| GTZC1SMEN | GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): GTZC1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GTZC1 clocks enabled by the clock gating during Sleep and Stop modes |
| BKPSRAMSMEN | BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software 0 (B_0x0): BKPSRAM clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): BKPSRAM clocks enabled by the clock gating during Sleep and Stop modes |
| ICACHESMEN | ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): ICACHE clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ICACHE clocks enabled by the clock gating during Sleep and Stop modes |
| DCACHE1SMEN | DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): DCACHE1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DCACHE1 clocks enabled by the clock gating during Sleep and Stop modes |
| SRAM1SMEN | SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): SRAM1 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM1 clocks enabled by the clock gating during Sleep and Stop modes |