LPDMA1SMEN=B_0x0, DAC1SMEN=B_0x0, ADC4SMEN=B_0x0, ADF1SMEN=B_0x0, PWRSMEN=B_0x0, LPGPIO1SMEN=B_0x0, SRAM4SMEN=B_0x0, GTZC2SMEN=B_0x0
RCC AHB3 peripheral clock enable in Sleep and Stop modes register
| LPGPIO1SMEN | LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): LPGPIO1 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPGPIO1 clock enabled by the clock gating during Sleep and Stop modes |
| PWRSMEN | PWR clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): PWR clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): PWR clock enabled by the clock gating during Sleep and Stop modes |
| ADC4SMEN | ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): ADC4 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ADC4 clock enabled by the clock gating during Sleep and Stop modes |
| DAC1SMEN | DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): DAC1 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): DAC1 clock enabled by the clock gating during Sleep and Stop modes |
| LPDMA1SMEN | LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): LPDMA1 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPDMA1 clock enabled by the clock gating during Sleep and Stop modes |
| ADF1SMEN | ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): ADF1 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ADF1 clock enabled by the clock gating during Sleep and Stop modes |
| GTZC2SMEN | GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): GTZC2 clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GTZC2 clock enabled by the clock gating during Sleep and Stop modes |
| SRAM4SMEN | SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 (B_0x0): SRAM4 clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM4 clocks enabled by the clock gating during Sleep and Stop modes |