BDRST=B_0x0, LSESYSEN=B_0x0, LSECSSD=B_0x0, LSEBYP=B_0x0, LSIRDY=B_0x0, RTCSEL=B_0x0, LSESYSRDY=B_0x0, LSERDY=B_0x0, LSEON=B_0x0, LSCOEN=B_0x0, LSION=B_0x0, LSECSSON=B_0x0, LSEDRV=B_0x0, RTCEN=B_0x0, LSCOSEL=B_0x0, LSEGFON=B_0x0, LSIPREDIV=B_0x0
RCC backup domain control register
| LSEON | LSE oscillator enable This bit is set and cleared by software. 0 (B_0x0): LSE oscillator off 1 (B_0x1): LSE oscillator on |
| LSERDY | LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles. 0 (B_0x0): LSE oscillator not ready 1 (B_0x1): LSE oscillator ready |
| LSEBYP | LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). 0 (B_0x0): LSE oscillator not bypassed 1 (B_0x1): LSE oscillator bypassed |
| LSEDRV | LSE oscillator drive capability This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode. 0 (B_0x0): ‘Xtal mode’ lower driving capability 1 (B_0x1): ‘Xtal mode’ medium-low driving capability 2 (B_0x2): ‘Xtal mode’ medium-high driving capability 3 (B_0x3): ‘Xtal mode’ higher driving capability |
| LSECSSON | CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable this LSECSSON bit. 0 (B_0x0): CSS on LSE OFF 1 (B_0x1): CSS on LSE ON |
| LSECSSD | CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32�kHz oscillator (LSE). 0 (B_0x0): No failure detected on LSE 1 (B_0x1): Failure detected on LSE |
| LSESYSEN | LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed. 0 (B_0x0): LSE can be used only for RTC, TAMP, and CSS on LSE. 1 (B_0x1): LSE can be used by any other peripheral or function. |
| RTCSEL | RTC and TAMP clock source selection This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the�backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them. 0 (B_0x0): No clock selected 1 (B_0x1): LSE oscillator clock selected 2 (B_0x2): LSI oscillator clock selected 3 (B_0x3): HSE oscillator clock divided by 32 selected |
| LSESYSRDY | LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. 0 (B_0x0): LSESYS clock not ready 1 (B_0x1): LSESYS clock ready |
| LSEGFON | LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). 0 (B_0x0): LSE glitch filter disabled 1 (B_0x1): LSE glitch filter enabled |
| RTCEN | RTC and TAMP clock enable This bit is set and cleared by software. 0 (B_0x0): RTC and TAMP clock disabled 1 (B_0x1): RTC and TAMP clock enabled |
| BDRST | Backup domain software reset This bit is set and cleared by software. 0 (B_0x0): Reset not activated 1 (B_0x1): Reset the entire backup domain. |
| LSCOEN | Low-speed clock output (LSCO) enable This bit is set and cleared by software. 0 (B_0x0): LSCO disabled 1 (B_0x1): LSCO enabled |
| LSCOSEL | Low-speed clock output selection This bit is set and cleared by software. 0 (B_0x0): LSI clock selected 1 (B_0x1): LSE clock selected |
| LSION | LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60��s maximum after the LSION bit is cleared. 0 (B_0x0): LSI oscillator OFF 1 (B_0x1): LSI oscillator ON |
| LSIRDY | LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After�LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. 0 (B_0x0): LSI oscillator not ready 1 (B_0x1): LSI oscillator ready |
| LSIPREDIV | Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 0 (B_0x0): LSI not divided 1 (B_0x1): LSI divided by 128 |