SPI1SEL=B_0x0, USART2SEL=B_0x0, USART3SEL=B_0x0, FDCAN1SEL=B_0x0, I2C4SEL=B_0x0, UART5SEL=B_0x0, USART1SEL=B_0x0, I2C1SEL=B_0x0, UART4SEL=B_0x0, SYSTICKSEL=B_0x0, SPI2SEL=B_0x0, LPTIM2SEL=B_0x0, I2C2SEL=B_0x0, ICLKSEL=B_0x0
RCC peripherals independent clock configuration register 1
| USART1SEL | USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 (B_0x0): PCLK2 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| USART2SEL | USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source. The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| USART3SEL | USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| UART4SEL | UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| UART5SEL | UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| I2C1SEL | I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): MSIK selected |
| I2C2SEL | I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): MSIK selected |
| I2C4SEL | I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): MSIK selected |
| SPI2SEL | SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 0 (B_0x0): PCLK1 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): MSIK selected |
| LPTIM2SEL | Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. 0 (B_0x0): PCLK1 selected 1 (B_0x1): LSI selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| SPI1SEL | SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 0 (B_0x0): PCLK2 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): MSIK selected |
| SYSTICKSEL | SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. 0 (B_0x0): HCLK/8 selected 1 (B_0x1): LSI selected 2 (B_0x2): LSE selected 3 (B_0x3): reserved |
| FDCAN1SEL | FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source. 0 (B_0x0): HSE clock selected 1 (B_0x1): PLL1“Q” (pll1_q_ck) selected 2 (B_0x2): PLL2 “P” (pll2_p_ck) selected 3 (B_0x3): reserved |
| ICLKSEL | Intermediate clock source selection These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC. 0 (B_0x0): HSI48 clock selected 1 (B_0x1): PLL2 “Q” (pll2_q_ck) selected 2 (B_0x2): PLL1 “Q” (pll1_q_ck) selected 3 (B_0x3): MSIK clock selected |
| TIMICSEL | Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected as�TIM16, TIM17, or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. 4 (B_0x4): HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 5 (B_0x5): HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 6 (B_0x6): HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 ,and LPTIM2 as internal input capture 7 (B_0x7): HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture |