SW=B_0x0, STOPKERWUCK=B_0x0, MCOSEL=B_0x0, SWS=B_0x0, STOPWUCK=B_0x0, MCOPRE=B_0x0
RCC clock configuration register 1
| SW | system clock switch This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK. 0 (B_0x0): MSIS selected as system clock 1 (B_0x1): HSI16 selected as system clock 2 (B_0x2): HSE selected as system clock 3 (B_0x3): PLL pll1_r_ck selected as system clock |
| SWS | system clock switch status This bitfield is set and cleared by hardware to indicate which clock source is used as system clock. 0 (B_0x0): MSIS oscillator used as system clock 1 (B_0x1): HSI16 oscillator used as system clock 2 (B_0x2): HSE used as system clock 3 (B_0x3): PLL pll1_r_ck used as system clock |
| STOPWUCK | wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on�HSE. STOPWUCK must not be modified when the CSS is enabled by HSECSSON in�RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE is�requested (SW�=�10). 0 (B_0x0): MSIS oscillator selected as wake-up from stop clock and CSS backup clock 1 (B_0x1): HSI16 oscillator selected as wake-up from stop clock and CSS backup clock |
| STOPKERWUCK | wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. 0 (B_0x0): MSIK oscillator automatically enabled when exiting Stop mode 1 (B_0x1): HSI16 oscillator automatically enabled when exiting Stop mode |
| MCOSEL | microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 0 (B_0x0): MCO output disabled, no clock on MCO 1 (B_0x1): SYSCLK system clock selected 2 (B_0x2): MSIS clock selected 3 (B_0x3): HSI16 clock selected 4 (B_0x4): HSE clock selected 5 (B_0x5): Main PLL clock pll1_r_ck selected 6 (B_0x6): LSI clock selected 7 (B_0x7): LSE clock selected 8 (B_0x8): Internal HSI48 clock selected 9 (B_0x9): MSIK clock selected |
| MCOPRE | microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 0 (B_0x0): MCO divided by 1 1 (B_0x1): MCO divided by 2 2 (B_0x2): MCO divided by 4 3 (B_0x3): MCO divided by 8 4 (B_0x4): MCO divided by 16 |