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STMicroelectronics /STM32U5Gx /RTC /ALRABINR

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Interpret as ALRABINR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS

Description

RTC alarm A binary mode register

Fields

SS

Synchronous counter alarm value in Binary mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data