STMicroelectronics /STM32U5Gx /RTC /MISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALRAMF)ALRAMF 0 (ALRBMF)ALRBMF 0 (WUTMF)WUTMF 0 (TSMF)TSMF 0 (TSOVMF)TSOVMF 0 (ITSMF)ITSMF 0 (SSRUMF)SSRUMF

Description

RTC non-secure masked interrupt status register

Fields

ALRAMF

ALRAMF

ALRBMF

ALRBMF

WUTMF

WUTMF

TSMF

TSMF

TSOVMF

TSOVMF

ITSMF

ITSMF

SSRUMF

SSRUMF

Links

()