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STMicroelectronics /STM32U5Gx /SAI1 /BCR2

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Interpret as BCR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FTH0 (FFLUSH)FFLUSH 0 (TRIS)TRIS 0 (MUTE)MUTE 0 (MUTEVAL)MUTEVAL 0MUTECN0 (CPL)CPL 0COMP

Description

B Configuration register 2

Fields

FTH

FIFO threshold
FFLUSH

FIFO flush
TRIS

Tristate management on data line
MUTE

Mute
MUTEVAL

Mute value
MUTECN

Mute counter
CPL

Complement bit
COMP

Companding mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data