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STMicroelectronics /STM32U5Gx /TIM15 /SMCR

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Interpret as SMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMS0TS_2_0 0 (MSM)MSM 0 (CC1DE)CC1DE 0 (SMS_3)SMS_3 0TS_4_3

Description

slave mode control register

Fields

SMS

Slave mode selection
TS_2_0

Trigger selection
MSM

Master/slave mode
CC1DE

Capture/Compare 1 DMA request enable
SMS_3

Slave mode selection
TS_4_3

Trigger selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data