Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/SiFive/sifive_hifive_unmatched_a00/sifive_i2c0_1/control#0x0
Control register
I2C core enable bit
I2C core interrupt enable bit
https://github.com/cmsis-svd/cmsis-svd-data