Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/SiFive/sifive_hifive_unmatched_a00/sifive_spi0_1/fmt#0x0
Frame format
SPI protocol
SPI endianness
SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise.
Number of bits per frame
https://github.com/cmsis-svd/cmsis-svd-data