Regviz

Spansion /MB9AFA3xL /LCDC /LCDC_PSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LCDC_PSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Fujitsu/MB9AFAAxL/LCDC/LCDC_PSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0 (CLKSEL)CLKSEL

Description

LCDC Clock Prescaler Register

Fields

CLKDIV

LCDC clock division ratio setting bit
CLKSEL

Source clock selection bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data