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Spansion /MB9AFB4xM /LCDC /LCDC_PSR

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Interpret as LCDC_PSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0 (CLKSEL)CLKSEL

Description

LCDC Clock Prescaler Register

Fields

CLKDIV

LCDC clock division ratio setting bit
CLKSEL

Source clock selection bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data