Spansion /MB9BF21xT /ETHERNET_MAC0 /TDLAR

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Interpret as TDLAR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STL2)STL2 0 (STL3)STL3 0 (STL4)STL4 0 (STL5)STL5 0 (STL6)STL6 0 (STL7)STL7 0 (STL8)STL8 0 (STL9)STL9 0 (STL10)STL10 0 (STL11)STL11 0 (STL12)STL12 0 (STL13)STL13 0 (STL14)STL14 0 (STL15)STL15 0 (STL16)STL16 0 (STL17)STL17 0 (STL18)STL18 0 (STL19)STL19 0 (STL20)STL20 0 (STL21)STL21 0 (STL22)STL22 0 (STL23)STL23 0 (STL24)STL24 0 (STL25)STL25 0 (STL26)STL26 0 (STL27)STL27 0 (STL28)STL28 0 (STL29)STL29 0 (STL30)STL30 0 (STL31)STL31

Description

Transmit Descriptor List Address Register

Fields

STL2

Bit2 of TDLAR

STL3

Bit3 of TDLAR

STL4

Bit4 of TDLAR

STL5

Bit5 of TDLAR

STL6

Bit6 of TDLAR

STL7

Bit7 of TDLAR

STL8

Bit8 of TDLAR

STL9

Bit9 of TDLAR

STL10

Bit10 of TDLAR

STL11

Bit11 of TDLAR

STL12

Bit12 of TDLAR

STL13

Bit13 of TDLAR

STL14

Bit14 of TDLAR

STL15

Bit15 of TDLAR

STL16

Bit16 of TDLAR

STL17

Bit17 of TDLAR

STL18

Bit18 of TDLAR

STL19

Bit19 of TDLAR

STL20

Bit20 of TDLAR

STL21

Bit21 of TDLAR

STL22

Bit22 of TDLAR

STL23

Bit23 of TDLAR

STL24

Bit24 of TDLAR

STL25

Bit25 of TDLAR

STL26

Bit26 of TDLAR

STL27

Bit27 of TDLAR

STL28

Bit28 of TDLAR

STL29

Bit29 of TDLAR

STL30

Bit30 of TDLAR

STL31

Start of Transmit List

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