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Spansion /MB9BF41xT /EXBUS /TIM0

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Interpret as TIM0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RACC0RADC0FRADC0RIDLC0WACC0WADC0WWEC0WIDLC

Description

Timing Register 0

Fields

RACC

Read Access Cycle
RADC

Read Address Setup cycle
FRADC

First Read Address Cycle
RIDLC

Read Idle Cycle
WACC

Write Access Cycle
WADC

Write Address Setup cycle
WWEC

Write Enable Cycle
WIDLC

Write Idle Cycle

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data