Regviz

Spansion /MB9BF46xx /CLK_GATING /MRST0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MRST0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Spansion/MB9BF36xx/CLK_GATING/MRST0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MFSRST0)MFSRST0 0 (MFSRST1)MFSRST1 0 (MFSRST2)MFSRST2 0 (MFSRST3)MFSRST3 0 (MFSRST4)MFSRST4 0 (MFSRST5)MFSRST5 0 (MFSRST6)MFSRST6 0 (MFSRST7)MFSRST7 0 (MFSRST8)MFSRST8 0 (MFSRST9)MFSRST9 0 (MFSRST10)MFSRST10 0 (MFSRST11)MFSRST11 0 (MFSRST12)MFSRST12 0 (MFSRST13)MFSRST13 0 (MFSRST14)MFSRST14 0 (MFSRST15)MFSRST15 0 (ADCRST0)ADCRST0 0 (ADCRST1)ADCRST1 0 (ADCRST2)ADCRST2 0 (ADCRST3)ADCRST3 0 (DMARST)DMARST 0 (EXBRST)EXBRST

Description

register MRST0

Fields

MFSRST0

bitfield MFSRST0
MFSRST1

bitfield MFSRST1
MFSRST2

bitfield MFSRST2
MFSRST3

bitfield MFSRST3
MFSRST4

bitfield MFSRST4
MFSRST5

bitfield MFSRST5
MFSRST6

bitfield MFSRST6
MFSRST7

bitfield MFSRST7
MFSRST8

bitfield MFSRST8
MFSRST9

bitfield MFSRST9
MFSRST10

bitfield MFSRST10
MFSRST11

bitfield MFSRST11
MFSRST12

bitfield MFSRST12
MFSRST13

bitfield MFSRST13
MFSRST14

bitfield MFSRST14
MFSRST15

bitfield MFSRST15
ADCRST0

bitfield ADCRST0
ADCRST1

bitfield ADCRST1
ADCRST2

bitfield ADCRST2
ADCRST3

bitfield ADCRST3
DMARST

bitfield DMARST
EXBRST

bitfield EXBRST

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data