Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Fujitsu/MB9BF61xT/USBETHERCLK/UPCR5#0x0
USB/Ethernet-PLL Control Register 5
Frequency division ratio (M) setting bit of the USB/Ethernet-PLL clock
https://github.com/cmsis-svd/cmsis-svd-data