stm32 /stm32c0 /STM32C011 /DMA /DMA_ISR

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Interpret as DMA_ISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GIF1 0 (B_0x0)TCIF1 0 (B_0x0)HTIF1 0 (B_0x0)TEIF1 0 (B_0x0)GIF2 0 (B_0x0)TCIF2 0 (B_0x0)HTIF2 0 (B_0x0)TEIF2 0 (B_0x0)GIF3 0 (B_0x0)TCIF3 0 (B_0x0)HTIF3 0 (B_0x0)TEIF3

GIF1=B_0x0, TEIF1=B_0x0, TCIF2=B_0x0, HTIF3=B_0x0, TCIF1=B_0x0, GIF3=B_0x0, TCIF3=B_0x0, TEIF3=B_0x0, TEIF2=B_0x0, HTIF2=B_0x0, GIF2=B_0x0, HTIF1=B_0x0

Description

DMA interrupt status register

Fields

GIF1

global interrupt flag for channel 1

0 (B_0x0): no TE, HT or TC event

1 (B_0x1): a TE, HT or TC event occurred

TCIF1

transfer complete (TC) flag for channel 1

0 (B_0x0): no TC event

1 (B_0x1): a TC event occurred

HTIF1

half transfer (HT) flag for channel 1

0 (B_0x0): no HT event

1 (B_0x1): a HT event occurred

TEIF1

transfer error (TE) flag for channel 1

0 (B_0x0): no TE event

1 (B_0x1): a TE event occurred

GIF2

global interrupt flag for channel 2

0 (B_0x0): no TE, HT or TC event

1 (B_0x1): a TE, HT or TC event occurred

TCIF2

transfer complete (TC) flag for channel 2

0 (B_0x0): no TC event

1 (B_0x1): a TC event occurred

HTIF2

half transfer (HT) flag for channel 2

0 (B_0x0): no HT event

1 (B_0x1): a HT event occurred

TEIF2

transfer error (TE) flag for channel 2

0 (B_0x0): no TE event

1 (B_0x1): a TE event occurred

GIF3

global interrupt flag for channel 3

0 (B_0x0): no TE, HT or TC event

1 (B_0x1): a TE, HT or TC event occurred

TCIF3

transfer complete (TC) flag for channel 3

0 (B_0x0): no TC event

1 (B_0x1): a TC event occurred

HTIF3

half transfer (HT) flag for channel 3

0 (B_0x0): no HT event

1 (B_0x1): a HT event occurred

TEIF3

transfer error (TE) flag for channel 3

0 (B_0x0): no TE event

1 (B_0x1): a TE event occurred

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