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stm32 /stm32c0 /STM32C011 /RCC /RCC_AHBENR

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Interpret as RCC_AHBENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMA1EN 0 (B_0x0)FLASHEN 0 (B_0x0)CRCEN

CRCEN=B_0x0, FLASHEN=B_0x0, DMA1EN=B_0x0

Description

RCC AHB peripheral clock enable register

Fields

DMA1EN

DMA1 and DMAMUX clock enable Set and cleared by software. DMAMUX is enabled as long as at least one DMA peripheral is enabled.

0 (B_0x0): Disable

1 (B_0x1): Enable
FLASHEN

Flash memory interface clock enable Set and cleared by software. This bit can only be cleared when the Flash memory is in power down mode.

0 (B_0x0): Disable

1 (B_0x1): Enable
CRCEN

CRC clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32