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stm32 /stm32c0 /STM32C011 /RCC /RCC_AHBRSTR

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Interpret as RCC_AHBRSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DMA1RST 0 (B_0x0)FLASHRST 0 (B_0x0)CRCRST

DMA1RST=B_0x0, CRCRST=B_0x0, FLASHRST=B_0x0

Description

RCC AHB peripheral reset register

Fields

DMA1RST

DMA1 and DMAMUX reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset DMA1 and DMAMUX
FLASHRST

Flash memory interface reset Set and cleared by software. This bit can only be set when the Flash memory is in power down mode.

0 (B_0x0): No effect

1 (B_0x1): Reset Flash memory interface
CRCRST

CRC reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset CRC

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32