SYSCFGEN=B_0x0, TIM1EN=B_0x0, TIM17EN=B_0x0, TIM16EN=B_0x0, TIM14EN=B_0x0, ADCEN=B_0x0, USART1EN=B_0x0, SPI1EN=B_0x0
RCC APB peripheral clock enable register 2
| SYSCFGEN | SYSCFG clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM1EN | TIM1 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| SPI1EN | SPI1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USART1EN | USART1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM14EN | TIM14 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM16EN | TIM16 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM17EN | TIM16 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| ADCEN | ADC clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |