LSERDYC=B_0x0, CSSC=B_0x0, HSERDYC=B_0x0, LSECSSC=B_0x0, LSIRDYC=B_0x0, HSIRDYC=B_0x0
RCC clock interrupt clear register
| LSIRDYC | LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear LSIRDYF flag |
| LSERDYC | LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear LSERDYF flag |
| HSIRDYC | HSI16 ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear HSIRDYF flag |
| HSERDYC | HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear HSERDYF flag |
| CSSC | Clock security system interrupt clear This bit is set by software to clear the HSECSSF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear CSSF flag |
| LSECSSC | LSE Clock security system interrupt clear This bit is set by software to clear the LSECSSF flag. 0 (B_0x0): No effect 1 (B_0x1): Clear LSECSSF flag |