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stm32 /stm32c0 /STM32C011 /RCC /RCC_CIER

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Interpret as RCC_CIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSIRDYIE 0 (B_0x0)LSERDYIE 0 (B_0x0)HSIRDYIE 0 (B_0x0)HSERDYIE

HSIRDYIE=B_0x0, LSIRDYIE=B_0x0, HSERDYIE=B_0x0, LSERDYIE=B_0x0

Description

RCC clock interrupt enable register

Fields

LSIRDYIE

LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:

0 (B_0x0): Disable

1 (B_0x1): Enable
LSERDYIE

LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:

0 (B_0x0): Disable

1 (B_0x1): Enable
HSIRDYIE

HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:

0 (B_0x0): Disable

1 (B_0x1): Enable
HSERDYIE

HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32