RTCSEL=B_0x0, LSEDRV=B_0x0, RTCRST=B_0x0, LSECSSON=B_0x0, LSEON=B_0x0, LSEBYP=B_0x0, LSERDY=B_0x0, LSECSSD=B_0x0, LSCOEN=B_0x0, LSCOSEL=B_0x0, RTCEN=B_0x0
RCC control/status register 1
| LSEON | LSE oscillator enable Set and cleared by software to enable LSE oscillator: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LSERDY | LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable): After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0 (B_0x0): Not ready 1 (B_0x1): Ready |
| LSEBYP | LSE oscillator bypass Set and cleared by software to bypass the LSE oscillator (in debug mode). This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 0 (B_0x0): Not bypassed 1 (B_0x1): Bypassed |
| LSEDRV | LSE oscillator drive capability Set by software to select the LSE oscillator drive capability as follows: Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode. 0 (B_0x0): low driving capability 1 (B_0x1): medium-low driving capability 2 (B_0x2): medium-high driving capability 3 (B_0x3): high driving capability |
| LSECSSON | CSS on LSE enable Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows: LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LSECSSD | CSS on LSE failure Detection Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE): 0 (B_0x0): No failure detected 1 (B_0x1): Failure detected |
| RTCSEL | RTC clock source selection Set by software to select the clock source for the RTC as follows: Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00. 0 (B_0x0): No clock 1 (B_0x1): LSE 2 (B_0x2): LSI 3 (B_0x3): HSE divided by 32 |
| RTCEN | RTC clock enable Set and cleared by software. The bit enables clock to RTC and TAMP. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RTCRST | RTC domain software reset Set and cleared by software to reset the RTC domain: 0 (B_0x0): No effect 1 (B_0x1): Reset |
| LSCOEN | Low-speed clock output (LSCO) enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LSCOSEL | Low-speed clock output selection Set and cleared by software to select the low-speed output clock: 0 (B_0x0): LSI 1 (B_0x1): LSE |