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stm32 /stm32f0 /STM32F0x1 /ADC /CFGR2

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Interpret as CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (JITOFF_D2)JITOFF_D2 0 (JITOFF_D4)JITOFF_D4

Description

configuration register 2

Fields

JITOFF_D2

JITOFF_D2
JITOFF_D4

JITOFF_D4

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32