Regviz

stm32 /stm32f0 /STM32F0x1 /ADC /ISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ISR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32f0/STM32F0x8/ADC/ISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADRDY)ADRDY 0 (EOSMP)EOSMP 0 (EOC)EOC 0 (EOS)EOS 0 (OVR)OVR 0 (AWD)AWD

Description

interrupt and status register

Fields

ADRDY

ADC ready
EOSMP

End of sampling flag
EOC

End of conversion flag
EOS

End of sequence flag
OVR

ADC overrun
AWD

Analog watchdog flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32