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stm32 /stm32f0 /STM32F0x1 /PWR /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPDS)LPDS 0 (PDDS)PDDS 0 (CWUF)CWUF 0 (CSBF)CSBF 0 (PVDE)PVDE 0PLS0 (DBP)DBP

Description

power control register

Fields

LPDS

Low-power deep sleep
PDDS

Power down deepsleep
CWUF

Clear wakeup flag
CSBF

Clear standby flag
PVDE

Power voltage detector enable
PLS

PVD level selection
DBP

Disable backup domain write protection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32