Regviz

stm32 /stm32f1 /STM32F100 /FLASH /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BSY)BSY 0 (PGERR)PGERR 0 (WRPRTERR)WRPRTERR 0 (EOP)EOP

Description

Status register

Fields

BSY

Busy
PGERR

Programming error
WRPRTERR

Write protection error
EOP

End of operation

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32