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stm32 /stm32f1 /STM32F100 /PWR /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPDS)LPDS 0 (PDDS)PDDS 0 (CWUF)CWUF 0 (CSBF)CSBF 0 (PVDE)PVDE 0PLS0 (DBP)DBP

Description

Power control register (PWR_CR)

Fields

LPDS

Low Power Deep Sleep
PDDS

Power Down Deep Sleep
CWUF

Clear Wake-up Flag
CSBF

Clear STANDBY Flag
PVDE

Power Voltage Detector Enable
PLS

PVD Level Selection
DBP

Disable Backup Domain write protection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32