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stm32 /stm32f1 /STM32F101 /AFIO /MAPR

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Interpret as MAPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI1_REMAP)SPI1_REMAP 0 (I2C1_REMAP)I2C1_REMAP 0 (USART1_REMAP)USART1_REMAP 0 (USART2_REMAP)USART2_REMAP 0USART3_REMAP 0TIM1_REMAP 0TIM2_REMAP 0TIM3_REMAP 0 (TIM4_REMAP)TIM4_REMAP 0CAN_REMAP 0 (PD01_REMAP)PD01_REMAP 0 (TIM5CH4_IREMAP)TIM5CH4_IREMAP 0 (ADC1_ETRGINJ_REMAP)ADC1_ETRGINJ_REMAP 0 (ADC1_ETRGREG_REMAP)ADC1_ETRGREG_REMAP 0 (ADC2_ETRGINJ_REMAP)ADC2_ETRGINJ_REMAP 0 (ADC2_ETRGREG_REMAP)ADC2_ETRGREG_REMAP 0SWJ_CFG

Description

AF remap and debug I/O configuration register (AFIO_MAPR)

Fields

SPI1_REMAP

SPI1 remapping
I2C1_REMAP

I2C1 remapping
USART1_REMAP

USART1 remapping
USART2_REMAP

USART2 remapping
USART3_REMAP

USART3 remapping
TIM1_REMAP

TIM1 remapping
TIM2_REMAP

TIM2 remapping
TIM3_REMAP

TIM3 remapping
TIM4_REMAP

TIM4 remapping
CAN_REMAP

CAN1 remapping
PD01_REMAP

Port D0/Port D1 mapping on OSCIN/OSCOUT
TIM5CH4_IREMAP

Set and cleared by software
ADC1_ETRGINJ_REMAP

ADC 1 External trigger injected conversion remapping
ADC1_ETRGREG_REMAP

ADC 1 external trigger regular conversion remapping
ADC2_ETRGINJ_REMAP

ADC 2 external trigger injected conversion remapping
ADC2_ETRGREG_REMAP

ADC 2 external trigger regular conversion remapping
SWJ_CFG

Serial wire JTAG configuration

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32