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stm32 /stm32f1 /STM32F101 /IWDG /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PVU)PVU 0 (RVU)RVU

Description

Status register (IWDG_SR)

Fields

PVU

Watchdog prescaler value update
RVU

Watchdog counter reload value update

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32