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stm32 /stm32f1 /STM32F101 /USART1 /CR2

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Interpret as CR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADD0 (LBDL)LBDL 0 (LBDIE)LBDIE 0 (LBCL)LBCL 0 (CPHA)CPHA 0 (CPOL)CPOL 0 (CLKEN)CLKEN 0STOP 0 (LINEN)LINEN

Description

Control register 2

Fields

ADD

Address of the USART node
LBDL

lin break detection length
LBDIE

LIN break detection interrupt enable
LBCL

Last bit clock pulse
CPHA

Clock phase
CPOL

Clock polarity
CLKEN

Clock enable
STOP

STOP bits
LINEN

LIN mode enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32